Integrated circuits (ICs) are commonly made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or field effect transistor (FET) features are shrunk to shrink corresponding device minimum dimensions including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions, e.g., channel layer depth, gate dielectric thickness, junction depths and etc. Shrinking device size increases device density and device performance, as well as reduces device operating conditions, i.e., chip and correspondingly, device supply voltages and voltage swings. Consequently, as a result of scaling otherwise seemingly neglectable device variations have caused serious design problems, especially in signal critical circuits such as memory cells and sense amplifiers.
A typical CMOS circuit, for example, includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND).
A typical static random access memory (SRAM) cell, ideally includes a balanced pair of cross coupled inverters storing a single data bit. A pair of pass gates (also ideally, a balanced pair of FETs) selectively connect the complementary outputs of the cross coupled inverter to a corresponding complementary pair of bit lines. A word line connected to the gates of the pass gate FETs selects connecting the cell to the corresponding complementary pair of bit lines. Normally, an N row by M column SRAM array is organized as N word lines by M column lines. Each column line includes one or more (K) bit line pairs that, in standby are clamped together and to a supply or reference voltage. Accessing Kbits (for a read or a write) from array entails driving one of the N word lines, turning on the pass gates for all M by K cells on that word line. With the pass gates on for that selected word line, the cross coupled cell inverters are coupled to the corresponding bit line pairs, partially selecting the M by K cells (half selected) on that word line. Selection of one of the M columns selects the K cells on that word line, the Kbits actually being accessed. The remaining (M−1) by K bits remain half selected during the access.
During a read, each cell on the selected word line couples its contents to its corresponding bit line pair such that each of the bit line pairs may rise/droop, usually, only to develop a small difference signal (e.g., 50 mV). While the bit line pairs in the selected K columns are unclamped and coupled to a sense amplifier, the half selected cells remain clamped together and to the reference voltage. At some point after sensing data for the selected K selected bits, the word line returns low again, deselecting/isolating the M by K cells on that word line. As long as the word line remains high, however, pass gates in half selected cells couple the reference voltage onto both storage nodes in each half selected cell. Depending upon the length of time that the word line remains high, the pass gates couple the partially selected cells tend toward an equilibrium point with the outputs of both of the cross coupled inverters (i.e., the storage nodes) being pulled toward a common voltage. This is normally a measure of cell stability, i.e., selecting the cell and clamping the bit lines to a voltage and noting the point at which the cell becomes meta-stable or switches, i.e., is upset. Unfortunately, imbalances in cell devices can upset half selected cells or at the very least to become meta-stable at normal design voltages. This instability is intolerable.
This instability may be worse still in a partially depleted (PD) silicon on insulator (SOI) CMOS SRAM cell, which is subject to what is known as floating body effects. Floating body effects, also known simply as body effects or as history effects, occur in completely or partially isolated devices, especially in analog logic circuit FETs, memory devices (FETs) or in logic where device body contacts may be infrequent or eliminated. As a particular device switches off, charge (i.e., majority carriers) remains in the device body beneath the channel. Device leakage and parasitic bipolar effects may add to the charge. Charge builds at isolated locations as the chip operates because the charge from fast switching devices is injected into locally isolated body pockets faster than it dissipates. Eventually, the injected charge reaches some steady state value that acts as a substrate bias, e.g., shifting the threshold voltage (VT) for the device. This steady state change depends upon each particular device's switching history and so is also known as the history effects for the particular device. So, body effects may cause two adjacent devices that are identical by design and measured to be identical to exhibit some difference, difference that may be time varying from changing circuit conditions, e.g., during read and write operations. Thus, the initial states of cell transistors (cell history) as well as gate-to-body tunneling current (that may further imbalance cell symmetry) can be critical to cell stability.
Thus, there is a need for improved SRAM cell stability, especially for PD SOI CMOS SRAMs.